At the GTC conference on March 22, Nvidia announced a partnership with Taiwan Semiconductor Manufacturing, ASML, and Synopsys to apply accelerated computing technology to computational lithography in chip manufacturing, as well as cuLitho, a software library for computational lithography.

Moore's Law is most often expressed as the number of transistors that can be contained in a semiconductor chip increases by multiple, and there are three important means to achieve the doubling of the number of transistors: increasing the chip area, reducing the size of components and optimizing the design of device circuits.

The reduction of component size is largely driven by the development of lithography process and technology. In the photolithography phase, the wafer is placed in a photolithography machine, where it is exposed to deep ultraviolet light (DUV). Light is projected onto the wafer through a "mask". The optical system of the photolithography machine shrinks the designed circuit pattern on the mask and focuses it onto the photolithography on the wafer. Print the pattern from the mask onto the photoresist coating.

This is not an easy job. Particle interference, refraction, and other physical or chemical defects can occur during the process, and the semiconductor manufacturer needs to correct the pattern on the mask to optimize the final exposure pattern. As chips get smaller and smaller, the resolution shrinks to nanometers, and the structure of the graphics projected onto the wafer deforms, computational lithography is needed to reconstruct the mask pattern.

Data show that computational lithography mainly uses software to model and simulate the entire lithography process, so as to optimize the shape of light source and mask plate, narrow the gap between lithography imaging and chip design, so as to achieve the desired state of lithography effect.

Thanks to advanced technologies such as computational lithography, Moore's Law continues, chips get smaller, and advanced process chips are produced. Today, foundries have begun mass production of 3-nanometer chips, and with the help of computational lithography, 2-nanometer chips will also be possible.

With cuLitho, TSMC can reduce prototype cycle time, increase wafer production, reduce energy consumption in chip manufacturing, and prepare for 2-nanometer chip production, Nvidia said. TSMC is expected to certify cuLitho in June this year, and will begin risky trial production of the 2-nanometer process in 2024 and mass production in 2025.

Two nanometers is not the end of chip production. In May 2022, IMEC (Microelectronics Research Center) announced the semiconductor technology and chip design path from less than one nanometer to two emm (A2). According to the plan, the industry is expected to start production of 0.2nm chips by 2036.

As chip sizes continue to shrink, the future development of computational lithography is broad. In addition, more advanced technologies are needed to realize the production of smaller chips, such as transistor technology. IMEC believes that the existing finFets can only be maintained to the N3 (3 nm) process, and then N2 (2 nm) and A14 (1.4 nm) will turn to GAA surround grid and Nanosheet nanosheet technology. Forksheet is used for the A10 (1 nm) and A7 (0.7 nm).