Research teams including the Tokyo Institute of Technology and AOI Electronics have developed a key technology to connect multiple semiconductor chips with different functions and make them work as one chip. This technology can improve the integration density and electrical characteristics of the chip and improve the yield.

In the past, the connections between cores were mostly made using an intermediate substrate called an Interposer. The main medium layer is silicon substrate, but this substrate has some problems in electrical characteristics, positioning accuracy, cost and so on.

The advantage of this technology is that the core can be connected with the core or the outside with the minimum number of elements. You can easily increase the core's integrated density or improve electrical characteristics, and you can easily position the connection. Another advantage is the ability to improve the high frequency characteristics and heat dissipation performance of the wiring that enables the core to achieve electrical connections to the outside.

At present, with the evolution of chip manufacturing process, due to the higher difficulty in design and implementation, the more complex process, the cost of the whole chip process design has increased significantly, and the "Moore's Law" is gradually slowing down.

In this context, Chiplet (a core or small chip) is expected to continue the "economic benefits" of Moore's Law from another dimension. It is believed that Chiplet can greatly improve the yield of large chips; It is beneficial to reduce the complexity and cost of design. It is expected to reduce the cost of making chips.

In March this year, semiconductor manufacturers such as AMD, Arm, ASE, Intel, Qualcomm, Samsung and TSMC, as well as more than ten technology industry giants such as Google Cloud, Meta and Microsoft jointly established the Universal Small Chip Interconnection (UCIe) industry Alliance, aiming at promoting UCIe technical standards and building a perfect ecosystem. Making it the future on-chip interconnection standard for heterogeneous packaged small chips, its members are leaders in semiconductor, packaging, IP suppliers, foundry, Chiplet design and many other fields.